4 cores/ ccx makes most sense since it's simplest and has fewest intra ccx connections and 8 would have a lot, but unless they planned for it back when they designed AM4 I'd question if they could go to a full chiplet design- with 2 4 core ccx- while staying with AM4. If they did plan for that I would be very impressed, and AMD did put a lot of stuff into the CPU package which would usually go into the chipset on the motherboard. That would also give an easy way to get 12 cores, threadripper had dummy ccx in gen 1 so you could get 12 core with 3x4 and one dummy.
I guess if they went the 8 core/ ccx route they'd have more failed chips to pad out the lower grade SKUs as well as 7nm probably being a bit less reliable as well; my skepticism comes from the extremely low relative failure rate for Zen1. We got a lot of 8 core 1600s here due to them running out of 'bad'/ partially failed chips.
Well, Intel is already offering 8-core CPUs that don't employ the CCX concept. It is more complex so probably more expensive to implement, but I don't think it would affect yields much. Plus the 7nm chiplets are approximately 1/3 the area of the 14nm chips, so that will offset much of the loss in yields of an immature 7nm process.
That said Voldemort has retracted his claim on the IO chip; Now he is claiming that these Ryzen 3 products use 7nm chiplets only. More likely that they have slightly larger 7nm chips with IO integrated for PCs, at maybe 1/2 the area of 14nm chips each. This also makes more sense with the combination with Navi which I think would have IO integrated because of bandwidth and energy requirements. Infinity Fabric 2 will do what, 100 GB/s between chips? That may be enough for an integrated GPU, but not for any discrete GPU nowadays.
The Intel 8 core is very expensive though, in part because you need to have 1x8 'perfect' cores when using ringbus rather than 2 perfect lots of 4 as with the infinity fabric/ ccx system; and it's also expensive on a very mature and refined node. Assuming linear error rates 8 core ccx would double the number of 'bad' ccxes (who knows though, depending on how the intra ccx stuff is handled complexity may go up non linearly and some stuff will have the same error rate whatever the core count). That might remain within acceptable levels, but it's all speculation at the moment.
At this point I'm not really sure what to make of the I/O situation at all. Too much rumour and I don't have the technical expertise to evaluate the relative likelihoods.